Generalization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip Master of Science Thesis

Since the late 1990's, the trend of integrated circuit design has been integrating several system components or IP blocks, such as processors and memories, on one chip. This is referred to the concept of System on Chip (SoC). However, with the increase of system scales in SoC systems, some problems such as inter-connection communication, scalability, system throughput and response time of the system have become the bottleneck of the system performance. To address these problems, researchers have proposed the concept of Network on Chip (NoC). To achieve guaranteed bandwidth (GB) QoS on NoC system, Nostrum NoC which is proposed by KTH uses a Time-Division-Multiplexing (TDM) Virtual Circuit (VC) mechanism. However, in the current simulator, the number of LNs for the switches in the network is fixed to 4 and can not be configured. This limits the bandwidth allocation granularity because a VC can only reserve the communication bandwidth in a multiple of 1/4 packets/cycle. The aim of this project is to generalize the slot table size from a fixed number to an arbitrary configurable number. Adopting the newly proposed concept of Logical Networks (LNs) instead of LNs, we expect the number of LNs can be generalized for each switch in the network. The number should be configured in the XML file which handles the configuration of the network and resources. After the generalization, the VCs in the network must still be free of contention. After the generalization extension is implemented on the simulator, five different test cases are used to fully guarantee that the extended simulator works correctly. Each test case focuses on a unique aspect of the VC configuration. The results of the test cases prove that the extension on the simulator have been successful.